The present invention relates to a semiconductor integrated circuit operated in sync with a clock signal and a technique effective when applied to a semiconductor integrated circuit having level sense type sequence circuits as a plurality of sequence circuits corresponding to clock supply destinations, for example.
When a semiconductor integrated circuit such as a microcomputer is designed, the design of a clock supply system for propagating a clock signal outputted from a clock generator configured as a clock supply source to a plurality of sequence circuits or the like corresponding to clock supply destinations is essential. The clock supply system has a clock wiring. The clock wiring is configured as a clock tree structure for propagating the clock signal to ends thereof via a plurality of branches. The clock wiring is designed so as to assume a fixed-width and fixed-length wiring for the purpose of attaining a reduction in clock skew. The clock skew refers to a shift in the phase between the clock signals at the plural clock supply destinations to which the clock supply source is common. The phase shift of the clock signal is also grasped as an arrival time difference in clock signal between the clock supply source and each of the clock supply destinations, i.e., a variation in the propagation delay time of the clock signal. As the plural sequence circuits connected to the ends of the clock wiring, may be mentioned edge trigger type sequence circuits in each of which the rising edge of the clock signal is brought to an input/output operating period, and level sense type sequence circuits in each of which a period during which the clock signal is of a high level, is brought to an input/output operating period.
A system using the edge trigger type sequence circuits is formed with a plurality of data paths including pre-stage edge trigger type sequence circuits each configured as the data transmission side, post-stage edge trigger type sequence circuits each configured as the data reception side, and combination circuits which are disposed between these edge trigger type sequence circuits and perform predetermined arithmetic processing or the like. In each of such data paths, the timing provided to allow the predetermined combination circuit to output the result of arithmetic operation might pass or go beyond the timing provided to change the rising edge of the clock signal supplied to the post-stage edge trigger type sequence circuit, i.e., the input/output operating period. In this case, the post-stage edge trigger type sequence circuit cannot fetch or take the result of arithmetic operation by the predetermined combination circuit, thus causing a MAX delay violation. As the cause of the MAX delay violation, variations in the amount of delay at each combination circuit and the like are also considered as well as the clock skew.
In order to relieve the MAX delay violation, there is considered a method for grasping the clock skew and the variations in the amount of delay at each combination circuit as design values every data path, for example at the design stage of the microcomputer and adjusting the change timing at the rising edge of the clock signal supplied to each post-stage edge trigger type sequence circuit on the basis of the design values after the manufacture of the microcomputer. However, the design values grasped at the design stage of the microcomputer are shifted from values grasped from the result of testing in a test process after its manufacture due to factors such as variations in manufacture, a drop in power supply voltage, etc., which cannot be grasped accurately at the design stage.
A non-patent document 1 (E. Takahashi, et al., “A post-silicon clock timing adjustment using genetic algorithms, ”2003 Symposium on VLSI Circuits Digest of Technical Papers, pp. 13-16) discloses a technique wherein in a system using edge trigger type sequence circuits, a variable delay circuit capable of changing a propagation delay time of a clock signal is disposed in the midstream of a clock wiring configured as a clock tree structure thereby to make it possible to adjust a clock skew according to the result of testing in a test process. According to the present technique, the amount of delay of a clock signal is changed by the variable delay circuit to adjust the timing provided to change the rising edge of the clock signal, thereby relieving a MAX delay violation.